How to give constraint for a input in FSM state machine

UVM
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Hi,

I have written verification test bench for a Mealy FSM 1011 sequence it is working fine but the output I am not able to get because 1011 sequence is not occurring once in an overall running of the test can anyone please suggest me how I can pass 1011 value as constraint to input.

Thanks in advance
Harsha

2

In reply to Harsha vardhan:

What does the testbench look like? How do you generate the stimulus? How do you apply the stimulus to the design? How do you know that 1011 does not occur? So many mysteries to solve.