How to get to know past value of some variable

SystemVerilog
,
1

In assertions there is $past function for this purpose.
What about outside assertions?

  1. can I use $past ?
  2. if not, how easily to get the same?

Update to question 1:

tried to use in agent monitor (UVM).
@(vif.rx[i]);
past_rx = $past(vif.rx[i], @(vif.rx[i])); // to get rx[i] value just
// before event @(vif.rx[i]);

Got compilation error messages:
** Error: /local/yuri/fulvous/tb_src/…//tb_src/hf_agent/hf_mon.svh(71): Automatic variables are not supported in clock expressions.
** Error: /local/yuri/fulvous/tb_src/…//tb_src/hf_agent/hf_mon.svh(71): automatic variables can not be used in ‘$past’.

2

In reply to Yurit:

You can use $past outside an assertion if you provide a sampling clock event. See section 16.9.3 Sampled value functions in the IEEE 1800-2017 SystemVerilog LRM.