Hi,
Can some tell me, is there any way to get address of a variable like in C?
In C, lets take a variable x. The address is given by &x. Same way do we have anything like that to get an address of a variable in SystemVerilog?
Hi,
Can some tell me, is there any way to get address of a variable like in C?
In C, lets take a variable x. The address is given by &x. Same way do we have anything like that to get an address of a variable in SystemVerilog?
In reply to janudeep3:
No, there are no pointers in SystemVerilog. SystemVerilog is based on Java, which is supposed to keep all references “safe”. That means you can never access a variable that has been de-allocated, or over-write another variable that you are not supposed to have access to.
If you could explain what you think you need to do with a pointer, someone could suggest an alternative approach.
In reply to dave_59:
Thanks Dave for the reply. I just wanted to know how the properties of an object are getting stored in a memory?
In reply to janudeep3:
There are getting stored in memory. What else do you need to know?