How to generate unique address from master to multiple slaves

SystemVerilog
2

In reply to raj@123:

class a;
  
  parameter N = 10; //no of slaves 
  
  rand int unsigned add[N];
  
  constraint unique_add { unique{add};}
  
  // if needed end address take another array of same size and add parameter(no of bytes) to the add array and use start and end address
  
  endclass

module tb;
  
  a a1;
  
  initial
    begin
      a1 = new;
      a1.randomize;
      $display("%p",a1.add);
      end
endmodule