SystemVerilog randomize address equal to 2 to the power of value?
addr or data = 1, 2, 4, 8, 16, … 32.
Without using constraint how we can create power of 2.
class packet;
rand bit [7:0]data;
rand bit [7:0]addr;
endclass
function bit gen_stim();
bit success, rd_wr;
success = std::randomize(addr, data, rd_wr);
return rd_wr ;
endfunction
module tb;
initial begin
packet pkt =new();
repeat(10) begin
success = std::randomize(rd_wr, addr ) with {rd_wr → 1<< addr;};
end
end
endmodule