How to generate a number with non-consecutive 1's

SystemVerilog
2

In reply to UVM_SV_101:


class c; 
    /* I want to constraint a 32 bit number to have count 1's ==12 and 1's should be non-consecutive. 
    I tried following but constraint solver failed. */ 

   rand bit[31:0]a;
 
  constraint c1{
     $countones(a) == 12;
     foreach(a[i])
     if(i>0 && a[i]==1) a[i-1] != a[i];
     }
endclass

module top; 
    timeunit 1ns/100ps;
    `include "uvm_macros.svh"
     import uvm_pkg::*;
     bit clk;  
     bit[31:0] a1;
     c c1; 
      
     initial forever #10 clk=!clk;  
      
     always  @(posedge clk)  begin 
     end 
     
       initial begin 
        c1=new(); 
         repeat(200) begin 
             @(posedge clk);   
             if (!randomize(c1)) `uvm_error("MYERR", "This is a randomize error");
             a1=c1.a;
             ap_12: assert property(@ (posedge clk) $countones(a1) ==12);  
             $display("a1=%b", a1); 
         end 
        
         $finish; 
        end  
 endmodule    
 # a1=10100100010101010010010101000100
# a1=10100101010101010000001010000101
# a1=10010101001010101010010000010001
# a1=10010010100101001010100100010010
# a1=10010100100101010000101010010100
# a1=10010101010000010101001010001010
# a1=10100100101000101000100101010010
# a1=00010100101010100101010010010100
# a1=01001010010101010101010001000100
# a1=01010010101000010001001010010101
# a1=01000101010101000100010100101010
# a1=01010100010010101010101000101000
# a1=10100100000010010101010101001001
# a1=00010100010100010100101010101010
# a1=10101000010101010001010100000101
# a1=01010010010010100101001001001001
# a1=00100010001010010101010010100101
# a1=01010001010010101000101000100101

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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