How to generate a 900 MHz clock

SystemVerilog
,
1

What is the best way to generate an exact 900MHz clock?

Currently this is what I am doing

`timescale 1ns/1ps

logic clk;
initial clk = 1’b0;
always #(1.111ns / 2) clk = ~clk;

Per waves, clk toggles every 0.556ns, so it has a period of 1.112ns, so it runs at a little under 900 MHz.

2

In reply to 1978bubun:

Change your code to

always begin
    #0.555ns clk = 1;
    #0.556ns clk = 0;
   end

or change your time precision to

`timescale 1ns/100fs