How to force dut internal signals in UVM environment

UVM
8

In reply to cooltoad:
Below is a link that I once used in a training class. I’ll emphasize certain points below.
I see this approach as a good way to drive interface signals.
http://systemverilog.us/vf/test_if_class.sv


interface dut_if(input logic clk);  // DO NOT USE!!!!!
	parameter hold_time   =3;  // 3ns  
	parameter setup_time  = 5;
	wire[31:0] data;
	logic[31:0] address;
	logic rd, wr; 
	clocking driver_cb @(posedge clk);
		default input #setup_time output #hold_time;
		output address;
		output rd, wr; 
		inout data;
	endclocking
	modport dut_mp(inout data, input clk, rd, wr, address);
	modport driver_mp(clocking driver_cb);
	ap_rdwr: assert property(@ (driver_cb)
		not(rd && wr));
	ap_addr_not0: assume property(@(driver_cb) $time> 20ns |-> address != 'h0);
endinterface : dut_if

class driver;
	virtual interface dut_if.driver_mp v_if; 
	transaction tx        =new(); 
	// driver
	task automatic drive();
		if(!randomize(tx))  $error("randomization failure"); 
		@ (v_if.driver_cb) begin
			if(!randomize(tx))  $error("randomization failure"); 
			v_if.driver_cb.rd                                  <= tx.rd; 
			v_if.driver_cb.wr                                  <= tx.wr; 
			v_if.driver_cb.address                             <= tx.address; 
			if(tx.wr)  v_if.driver_cb.data  <= tx.data_dr;   
			else  v_if.driver_cb.data  <=  'hZ; 
		end
	endtask : drive
endclass : driver
Notice the 3 ns delays in the outputs. 
http://systemverilog.us/vf/noforce.png

// ***** On the force, I tried 
task automatic drive();
		if(!randomize(tx))  $error("randomization failure"); 
		@ (v_if.driver_cb) begin
			if(!randomize(tx))  $error("randomization failure"); 
			...
			if(tx.wr)  
				//v_if.driver_cb.data  <= tx.data_dr;  
			    force v_if.driver_cb.data  = tx.data_dr;  
			else  v_if.driver_cb.data  <=  'hZ; 
		end
	endtask : drive 
// **** ERROR MESSAGE
 Variables accessed through virtual interface cannot be used in continuous assignments.

Thus, go over my example and see if that works for you. I feel it is a better and cleaner approach, and more a la UVM.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr