How to force dut internal signals in UVM environment

UVM
7

Hello, I am facing a similar issue. The “force” solution works for me but since the force and the clocking edge arrive at the same time, this leads to a race-condition in the design. I tried fixing that by adding default output skew to the clocking block but that didn’t help. Should the skew be applied to the force statement? Or it is only applicable to non-blocking assignments?

Here is the code,

interface drv_sig(input bit clk);

bit force_enable;
bit drv_sig;

clocking drv_cb @(posed clk);
  input force_enable;
  output drv_sig;
endclocking

modport driver(
  clocking drv_cb,
  input clk,
  input force_enable,
output drv_sig);


always @(posedge clk) 
   if(force_enable != $past(force_enable)) begin
      if(force_enable == 1)
         force top.dut.data = drv_sig;
      else
         release top.dut.data;
    end

endinterface

Appreciate any input.