How to force dut internal signals in UVM environment

UVM
3

In reply to ben@SystemVerilog.us:

Another option is to use the force. Maybe more of what you want

interface dut_if(input bit clk);
    bit cntrl_enb;       // from control 
    logic [7:0] cntrl_data; // from control 
     
    //assign top.dut1.data= cntrl_enb ? cntrl_data : 'Z; 
    always @ (posedge clk)
        if(cntrl_enb)
          force top.dut1.data= cntrl_data;  // cntrl_enb ? cntrl_data : 'Z;
        else release top.dut1.data;

endinterface 

module dut(input bit clk); 
    // wire [7:0] data;
    logic [7:0] data;
endmodule : dut

module top; 
    bit clk;
    dut dut1(.*); 
    dut_if dut_if1(clk); 
endmodule

Ben SystemVerilog.us