I want to force some internal signals in DUT. If I put the internal signals in a interface, can I use like " assign if.internal = 1’b1 " ? Does this value have a conflict with real internal value? I mean the signal “internal” will have two drives.
What you are suggesting would work, but the internal signal would have to be a wire.
The problem with your approach is that it makes your DUT unclean since it inserts TB signals into your synthesizable design.
A better approach would be to have the assign into that internal signal from the interface under the control of the testbench. I demonstrate that below. The “cntrl_enb” and “cntrl_data” are issued by the testbench (e.g., the driver).
interface dut_if(input bit clk);
bit cntrl_enb; // from control
logic [7:0] cntrl_data; // from control
assign top.dut1.data= cntrl_enb ? cntrl_data : 'Z;
endinterface
module dut(input bit clk);
wire[7:0] data;
endmodule : dut
module top;
bit clk;
dut dut1(.*);
dut_if dut_if1(clk);
endmodule
Ben Cohen SystemVerilog.us