How to force/deposit string path in system verilog?

SystemVerilog
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3

In reply to dave_59:

Thanks dave. I understood that, string datatype can not converted to integral type/reg only using system verilog. But can i do reverse? I have instance path(reg/intergral type) and can i convert that in to string using some beauty of system-verilog? Please suggest if any alternate ways are there to do this?

Thanks and Regards,
Mitesh Patel