How to force/deposit string path in system verilog?

In reply to mitesh.patel:

There is nothing within the SystemVerilog language that allowed you to convert a string to identifier reference. The only possibility involves use of the VPI C interface.

Since you are already using SystemVerilog, there is nothing preventing you from using UVM and its VPI code. You can even specifically import the routines you want to use without importing the whole package.

Other options are using tool specific commands to do the force, or copying the UVM code for your own use (I’m mentioning that, but not recommending that).