In reply to dave_59:
Thank you Dave, I removed objections, still never stop. So I add delay #1;
I’m not sure whether adding delay is correct or not.
Now I’m referencing AnalysisConnections | Verification Academy
there is no Delay implemented in.
task run_phase( uvm_phase phase );
alu_txn before_txn, after_txn;
forever begin
before_fifo.get(before_txn);
after_fifo.get(after_txn);
if (!before_txn.compare(after_txn)) begin
`uvm_error("Comparator Mismatch",
$sformatf("%s does not match %s", before_txn.convert2string(), after_txn.convert2string()))
m_mismatches++;
end else begin
m_matches++;
end
end
endtask
If I add delay, analy_fifo.get(trans); is working as my expectation.
But why do I need to add the # dealy ? even the referencing code does not implemented # delay code.
If I get rid of Delay then it never stop.
//component_b
///...
forever begin
#1; //<== ???
`uvm_info(get_type_name(), $sformatf(" FIFO used: %0d", analy_fifo.used()), UVM_LOW)
if(analy_fifo.is_empty()) begin
`uvm_info(get_type_name(), "FIFO is Empty!!!!!",UVM_LOW)
end
else begin
analy_fifo.get(trans);
`uvm_info(get_type_name(),$sformatf(" Printing receive trans, \n ",trans.sprint()),UVM_LOW)
end
end