How to find a bug in this scenario

SystemVerilog
1

Hi There,

Let’s say I have a memory, of where the bug is if I am going to write data to location 10 internally due to a decoding logic issue it is going to write at a different location even when we are reading we are getting the right data from the same location. The question is how we are going to find the bug in this scenario.

I try to write a scoreboard checker but anyway, we are getting the correct data so we are not able to find the bug.

If it is white box verification I think we can write an assertion to verify the decoding logic.

I am thiniking in this way. am I right? Can anyone help me? to think in the right direction if I am wrong.

2
3

You could check by doing a standard frontdoor write to the memory location then a backdoor read from the same location and compare values. Conversely do a backdoor write to the memory location then a standard frontdoor read from the same location and compare values. For example:

reg [DATAWIDTH-1:0] array [ADDRWIDTH-1:0];
:
array.write(write_data, addr);    //Frontdoor
read_data=array[addr];            //Backdoor
if (write_data == read_data)
   $display("success");
else
   $display("fail");