How to do a parametrizable access to a bit slice

SystemVerilog
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5

In reply to Rahulkumar Patel:

Hi,

That’s exactly what I meant by C-style bit slice assignment, using an inverted mask and logical ‘or’. The thread was triggered from a discussion we had within our team about whether there was a better way of doing bit slice assignment in SystemVerilog - most of people use indeed C-Style assignment.
C-style assignment works perfectly but it’s far less readable than:
vector[msb:lsb]=new_slice_value;
Unfortunately this previous statement only works when msb and lsb are constant (not const int as documented by Dave previously).