How to do a parametrizable access to a bit slice

SystemVerilog
,
4

In reply to sylvainb:

If you want to avoid the loop for assigning every bit one by one.

function bit[31:0] assign_value (
                                    input bit [31:0] initial_value,
                                    input bit [31:0] assigned_field,
                                     int        lsb,
                                     int        msb);
      int tmp;
      assign_value = initial_value;
      
      tmp  = ((1<<(msb-lsb+1))-1) << lsb;
      assign_value = (assign_value & ~tmp) | assigned_field << lsb;
  
endfunction : assign_value