How to do a parametrizable access to a bit slice

SystemVerilog
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3

Hi Dave,

Thank you for your answer, I was actually looking for a solution that was more elegant and more “SystemVerilog” than using C style for assigning a slice…

By C Style I mean:

`define CTRL_RD_WR_MASK                  'hF
`define CTRL_RD_WR_READ_FUSE             'h1
rd_data = (rd_data & ~`CTRL_RD_WR_MASK ) | ( `CTRL_RD_WR_READ_FUSE & `CTRL_RD_WR_MASK);

By SystemVerilog style I was hoping using the associative arrays of const int defined in my 1st post and the expression:

rd_data[offset_table["CTRL_RD_WR"].offset+:offset_table["CTRL_RD_WR"].size] = CTRL_RD_WR_READ_FUSE;

The only solution I see now, if I want to avoid the loop for assigning every bit one by one is to use of preprocessor `define values or (local)parameters… Unfortunately I cannot pack those into associative arrays (unlike const int).