How to display `define PATH

SystemVerilog
1

Hi,

In my testbench, I have written like



`ifdef MOD_A
  `define HIER_PATH $root.x.y.a
`elsif MOD_B
  `define HIER_PATH $root.x.y.b
`elsif MOD_C
  `define HIER_PATH $root.x.y.c
`else
  `define HIER_PATH $root.xxx
`endif

From Makefile, I am defining MOD_A or MOD_B or MOD_C.

Now question is, How can I print the hierarchy path in testbench.

I want functionality somewhat like

$display("My Path is : %0s", `HIER_PATH);

But I am getting error.

2

In reply to electron:

`define QUOTE(s) `"s`"

$display("My Path is : %0s", `QUOTE(`HIER_PATH));
3

In reply to electron:

Hi Electron
You could also protect your defines with double quotes

define XX "$root.happy" module top (); initial $display(XX);
endmodule: top

4

In reply to mallick1:
That will not work if the intent is to use `HIER_PATH to select a signal.

`HIER_PATH.signal

5

In reply to dave_59:

Thanks dave
That’s right the ` is required to override the usual lexical meaning of "

Soummya