How to disable RAL registers creation from env

In reply to sameermsa:

uvm_coverage_model_e is a builtin masking mechanism in the UVM for controlling construction of the coverage model, which can mirror the register model. There is no similar mechanism for controlling the construction of registers. The code generator that builds the register model would have to implement that for you, or you have have to manually modify the code to put such a mechanism in place yourself.