How to detect z

SystemVerilog
1

What is logic to detect z ?

if (data == z)

is this right logic ?

2

In reply to keshav_chokshi:

If you want to check that all the bits in data are z, you can write

if (data === 'z)

If you want to check that any bit in data is z, use the $countbits function

if ($countbits(data,'z))
3

In reply to dave_59:

In reply to keshav_chokshi:
If you want to check that all the bits in data are z, you can write

if (data === 'z)

If you want to check that any bit in data is z, use the $countbits function

if ($countbits(data,'z))

I think === is not sythesizable in design. Can I use this logic in DUT?

4

In reply to keshav_chokshi:

The X and X states are simulation abstractions and synthesis tools do not support detection of these states.