How to detect "simulation step" event

SystemVerilog
,
1

I want to calculate time between simulation cycles. It could be some event triggered each time any change in the system is scheduled.
Something like code below, but functional.

module cycle_detect;
	longint sim_time;
	always @* begin 
		sim_time = $time;
	end
endmodule
2

In reply to toprunner:

There is no way to do what you ask within the SystemVerilog language. Without knowing what you are attempting to achieve, this is an XY problem.

Realize that there is no way to schedule something to happen after the last event in current the time step has happened because that would no longer be the last event.