How to detect number of one's in an array and each time one bit should be asserted and the remaining bits should be 0's by using SV constraints?

Assume that there is an array of 4 bit size eg: c[3:0] and every time one bit should be 1 and remaining bits should be 0’s and it should display number of 1’s in that array.

In reply to dinakarkuchi9:

You can the the system functions in SystemVerilog anywhere, in SAV, procedural blocks, constraints:

  1. $onehot(expression) returns `true (bit 1’b1) if only one bit of the expression is high.
  2. $onehot0(expression) returns `true (bit 1’b1) if at most one bit of the expression is high. This is equivalent to $onehot(expression) || expression==0
  3. $isunknown(expression) returns `true (bit 1’b1) if any bit of the expression is X or Z. This is equivalent to ^(expression) === ’bx.
  4. $countones (expression) returns the number of ONEs in a bit vector expression. X and Z values are not counted towards the number of ones.
  5. $countbits(expression, list_of_control_bits) // list used to identifies which values to count list_of_control_bits ::= control_bit { , control_bit } $countbits returns (as an int)the number of bits that have a specific set of values (e.g., 0, 1, X, Z) in a bit vector. For example, [1] $countbits (expression, '1, '0) returns the number of bits in expression having values 1or 0. $countbits (expression, 'x, 'z) returns the number of bits in expression having values X. or Z.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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