How to detect glitch using assertions?

SystemVerilog
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5

In reply to Reuben:

Hi Reuben,

Glitch can also be at positive value for req, in that case, you need to use something like this,

@(req)
  (1, first_change = $time) |=> (($time-first_change) <= duration)[*1:$];

I’ve tried with property as above, and it works for multiple glitch as well. If not same for you, can you provide a condition to experiment with?

Another way to detect negative glitch is,

property glitch_p;
  time t1;
  time t = 3;

  @(req)
    (!req, t1 = $time) |-> (req)[=1] ##0 (($time - t1) <= t);
endproperty