In reply to Tudor Timi:
Hi Tudor,
The assertion is checking the output of an 8-bit switch/mux. (I just put req but it is actually an 8-bit bus). This output will be fed to analog switch die. Therefore, glitch can’t happen on this output since a change on this value will change the selected signal of the analog die abrutply.
The reason why I decided to allow a glitch within the first 3ns is because of the inevitable wire delays that are present during gate level simulation. Then after this period, glitch should not happen because the selected signal of the analog die should not change abruptly. So my plan is after a posedge of clk, glitch can happen within 3ns, then after this period, glitch should not happen. The concurrent assertion will repeat for every posedge of clk.
About the “static” tools you mentioned, can you expound on this? I read something that formal verification tools can detect glitches, but I don’t understand how. I’m not that familiar in formal verification.
Thank you.
Regards,
Reuben