How to define a condition for a covergroup (using iff)?

SystemVerilog
16

In reply to dave_59:

In reply to Rahulkumar Patel:
You can collect coverage, but the calculation is incorrect.
The problem here is the bin gets created unconditionally, but is never incremented. If the expression is false at a sampling point, the count for the bin is not incremented.

Yes,bin gets created unconditionally.
Bin is incremented if expression is true and is not incremented when expression is false.


module check_cov; 

  int XYZ,PQR;
  int type_a;
  
  covergroup cg;
      cp : coverpoint type_a { 
                      bins out_bound_pqr[2] = {[37:38]} iff(type_a == PQR);
                      bins out_bound_xyz[3] = {[10:12]} iff(type_a == XYZ);
                       }
  endgroup
  
  cg m_cg;
  
  initial 
  begin
  XYZ = 0; type_a=10;  PQR = 0;
  m_cg = new();
  #5; PQR=0; XYZ=10; type_a=10; m_cg.sample(); #10; $display("COV : %f", m_cg.get_coverage()); // 20%
  #5; PQR=0; XYZ=15; type_a=10; m_cg.sample(); #10; $display("COV : %f", m_cg.get_coverage()); // 20% No change
  #5; PQR=37; XYZ=10; type_a=37; m_cg.sample(); #10; $display("COV : %f", m_cg.get_coverage()); // 40% 
  $finish;
  end 

endmodule


//output as expected: 
COV : 20.000000
COV : 20.000000
COV : 40.000000