In reply to Rahulkumar Patel:
You can collect coverage, but the calculation is incorrect.
If the expression is false at a sampling point, the count for the bin is not incremented.
The problem here is the bin gets created unconditionally, but is never incremented.
In reply to darp4u:
You can use `define for anything&mdash the macro pre-processor does not care about SystemVerilog syntax. But the end result has to be valid SystemVerilog to finish compilation.