How to declare virtual interface with params in the top module (in the testbench)?

UVM
,
1

I have the following Parameterised interface :

interface axi_interface #(parameter DATA_SIZE = 0)
  (input bit ACLK, input bit ARESETn);
   //write address channel signals
   logic [3:0]  AWID; //
   logic [31:0] AWADDR;
   .....
   .....
endinterface

I try to declare this interface as virtual interface in the top module (in the testbench)

module girobo2_tb_top;
   .....
   .....
   axi_interface #(.DATA_SIZE(63)) axi_vif(tb_axi_clk, axi_arstn);
   .....
   .....
endmodule

But I got the following error when I try to run the simulation:

** Error: (vsim-7065) …/sv/girobo2_tb_top.sv(245): Illegal assignment to type ‘virtual axi_interface’ from type ‘interface axi_interface #(.DATA_SIZE(63))’: Vir. ‘axi_interface’ interface must be assigned a matching interface or virtual interface.

2

In reply to saritr:

Are you using any methodology package ? If you are using UVM then while setting interface in config_db , you require to give actual type of virtual interface with same parameter.


uvm_config_db#(virtual axi_interface #(63)) :: set (,,,,);

“virtual axi_interface” type is having default parameter(i.e DATA_SIZE = 0) so you can not assign axi_vif (actual interface pointer) to this type. You have to change type to “virtual axi_interface#(64)”

3

In reply to kerulmodi:

What about the decleration?

4

In reply to saritr:

If you are declaring interface as virtual then use following syntax.

 virtual axi_interface #(.DATA_SIZE(63)) axi_vif; // virtual interface declaration..

You have declared active interface correctly in top module.
This error comes when interface assignment is having type conflict.

Check your interface assignment and make sure you have declared virtual interface with correct value of parameter.

Regards
Kerul Modi