How to deal with hdl_path with escape identifier

SystemVerilog
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1

hi:
I encountered a problem where the path of a certain signal contains \ due to dft. I tried the following approaches, but none of them worked.


1: assign vif.xx = tb_top.dut.U_ap_top.\g_core[0].xx
2: assign vif.xx = tb_top.dut.U_ap_top.\\g_core[0].xx
2

In reply to jianfeng.he:

What does ‘none of them worked’ mean? Did you get a syntax error? Did it compile and not give the results you are expecting?

3

In reply to jianfeng.he:

Verilog escaped identifiers require a white space character to terminate. Neither the leading backslash, nor the whitespace are considered part of the identifier. Without seeing your complete example, but I’m guessing this would work:

assign vif.xx = tb_top.dut.U_ap_top.\\g_core[0] .xx

(Note the space)

4

In reply to cgales:

In reply to jianfeng.he:
What does ‘none of them worked’ mean? Did you get a syntax error? Did it compile and not give the results you are expecting?

Reported an error similar to “path not found”.

5

In reply to Mark Curry:

In reply to jianfeng.he:
Verilog escaped identifiers require a white space character to terminate. Neither the leading backslash, nor the whitespace are considered part of the identifier. Without seeing your complete example, but I’m guessing this would work:

assign vif.xx = tb_top.dut.U_ap_top.\\g_core[0] .xx

(Note the space)

Thank you for your help, this works well