How to create template object in hierarchical seeding?

One way to control SystemVerilog’s hierarchical seeding is to create template objects, which are
used to generate all the random stimulus. As long as all calls to the random number generator
are only made via the template object(s), then the order of random seeds will be preserved since
SystemVerilog guarantees object random stability. Likewise, if the template object is initially
seeded in a control manner, then changes to the rest of the testbench will not affect it. An easy
way to control the seeding of a template object is to restrict the verification environment to one
initial block, which always gets the same seed, and then create the template object first thing at
time zero before any other calls to new or the RNG.

can anyone give the example how template object works ?

In reply to Urvi Patel:

Hi Urvi,

The idea of a template object is that you continue to re-use the same object over and over again, which maintains the object’s RNG seeding. For example,

myobject  obj;
...
obj = new();    // Object seeded from parent thread

obj.randomize();
// Use object values - .clone() if necessary
obj.randomize();
// Use object values - .clone() if necessary
obj.randomize();
// Use object values - .clone() if necessary

and so on. This is illustrated in Figure 5 of the paper you quoted from above. The idea is that you randomize one object so that you can control the seeding and maintain your random stability. VMM refers to this as a ‘data factory’ so that’s another way of thinking about it. This template object is your factory that you clone over and over again. Have a look at Figure 5 again for details, or take advantage of the built in random stability of UVM, which eliminates the need for a template object.

Best regards,
-Doug

Thanx Doug,

I have another query that is this a similar to statically declared initializer? What is the difference between statically declared initializer and template object?

In your explanation code ,
myobject obj;

obj = new(); // Object seeded from parent thread

this declaration is statically declared in package or module?

In reply to Urvi Patel:
The difference is that the template object gets constructed if and when it is needed. A static initializer always executes once at time 0.

Hi,

how to use $random to seed $random in system verilog?

In reply to Urvi Patel:
Do not use $random in SystemVerilog. Use $urandom