How to create random dynamic 2D arrays in SystemVerilog?

SystemVerilog
,
3

In reply to Shashank Gurijala:

I got the same error.

class frame_packet;
  rand int width;
  rand int height;
  rand int data[][];

  constraint size_con {
    width   inside {[8:2048]};
    height  inside {[8:1592]};
    data.size == width;
    foreach(data[width])
        data[width].size == height;

  }
endclass

module test;

initial begin
  frame_packet pkt;
  pkt = new();
  assert(pkt.randomize());
  foreach(pkt.data[i,j]) begin
    $display("data=%0d", pkt.data[i][j]);
  end
end

endmodule