How to constraint variables with randc.(random-cyclic)?Am unable to get proper behavior of randc

UVM
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1

I have declared the pkt_length variable as randc type.then i gave range for that variable with constraint.but it giving repeated values inside boundary only(means inside range only).
here my requirement was i need to do randomized the pkt_length with 255 times.but it getting repeated values only.
here small piece of code…

class ab_pkt extends uvm_sequence_item; 
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.
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   randc bit [15:0] pkt_length;
   constraint pkt_length_c{
	                     (pkt_length[15:8] inside {[8'h00:8'hFF]});
                          }
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endclass

i have used that one in my sequence like below…

class ab_base_seq extends uvm_sequence #(ab_pkt);
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  `uvm_do_with(req,{req.m_hwrite == 1;req.m_hburst == SINGLE;req.m_haddr == `PKT_REG;req.m_hwdata == req.pkt_length;})
		`uvm_info(get_type_name(), $sformatf("PKT LENGTH Reg = %h", req.pkt_length),UVM_LOW)
.
.
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endclass

am repeating this sequence from testcase 255 times.

is there any other method to do that pkt_length randomization from 0 to 255.without repeating same value…?

thanks,

2

In reply to Rao.Bee:

The randc directive only works on the same object randomized with the same constraints. The uvm_do macro creates a new object each time its used. You can either avoid using the uvm_do macro (See Sequences/Generation | Verification Academy) or you will have to build a list of previous pkt_length values and add another constraint
!(pkt_length inside {list};.

3

In reply to dave_59:

thanks dave.

in my case i cant remove uvm_do macro.
if i need to create pkt_length list…i need to write 0,1,2,3,…255.
is it good to write like that…in constraint …?

4

In reply to Rao.Bee:

A more simple solution is to run the loop in the sequence and starting this sequence in the test. Running the loop in the test complicates your problem.

5

In reply to chr_sue:

thanks chr_sue,

am unable to give loop in sequence due to some protocol issue …means it is changing my scenario…!

is it good to have unique constraint…?

6

In reply to Rao.Bee:

I do not understand that the loop in the sequence should have any influence on the protocol. The protocol behavior is only definde by the driver.
BTW why do you ues the randc declaration? It should also work with a simple rand declaration.
The uniqie does nor solve your issue. Because you are egnerating in your sequence only 1 seq_item. In any case this is unique.

7

In reply to chr_sue:

thanks chr_sue,
actually that particular sequence used for other testcases also.so all the testcase may not require for_loop.
so i need to take care about that sequence.

testcase only there in my hand.

8

In reply to Rao.Bee:

You could extend the current sequence, creating only 1 seq_item to another one which has a for loop inside.
The typical approch is to select for a testcase any sequence, creating/randomizing it and sdtarting this sequence on the corresponding sequencer.

9

In reply to Rao.Bee:

You can add a unique constraint to your `uvm_do_with macro.

  `uvm_do_with(req,{m_hwrite == 1;m_hburst == SINGLE;m_haddr == `PKT_REG;m_hwdata == pkt_length; unique {pkt_length, list}; })
list.push_back(req.pkt_length);
		`uvm_info(get_type_name(), $sformatf("PKT LENGTH Reg = %h", req.pkt_length),UVM_LOW)
.

Just remember the pain using the `uvm_do macros causes as you try to add more complexity and avoid it.

10

In reply to dave_59:

thanks dave ,
now am able to do proper randomization.