How to connect ports(which is defined as input or output array) when instantiate

SystemVerilog
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3

In reply to philerpeng:

Regardless of the value of NUM_SLAVES, your input port sig_a is an unpacked array expecting to be connected to an unpacked array, even if only one element. Unpacked arrays are stronger types than packed arrays which don’t care about number of matching bits in an assignment.

You need to use an array assignment pattern or a concatenation with the proper number of array elements:

     .sig_a ( { inst_B.sig_b } ),