How to connect ports(which is defined as input or output array) when instantiate

SystemVerilog
,
2

In reply to philerpeng:

I don’t think you can use like that in verilog.
Please try:


// Module A
module A #(parameter NUM_SLAVES = 1) (
input [NUM_SLAVES-1:0] sig_a
);
endmodule

// Module B
module B (
output sig_b
);
endmodule

// Module C
module C ();
 wire sig;
 B inst_b(.sig_b(sig));
 A #(1) inst_A (.sig_a (sig));
endmodule