Hi,
I have an UVM environment with OVM components. I face 2 issues that I’m not sure how to solve:
1). connect an OVM analysis port to my toplevel UVM analysis port (OVM monitor to topleevl UVM scoreboard)
2). do a set config object where the toplevel configuration is UVM and the subconfigurations are OVM
Any hint would be really appreciated!
Thanks!
It’s not possible to do it that way. See How to run the system verilog test or OVM test cases in UVM environment. if its possible? | Verification Academy
If you can keep the two environments completely independent of each other, you can call both uvm_pkg::run_test() and ovm_pkg::run_test() to build those environments. Note that you can never import both packages into the same scope.
OVM config objects must be derived from ovm_object, but uvm_config_db objects can be of any type. So you can make your UVM config object derived from ovm_object as long as your config object does not need any features from UVM. Other wise you will have to create two configuration objects and copy the data from one two the other and do not make any further changes to the config object.
You cannot connect an OVM component to a UVM component, but you can make an adapter class that receives an OVM transaction, converts it to a UVM transaction and then sends it on to the UVM scoreboard.
In the end, it just might be easier to convert the OVM to UVM.
Dave