Hi,
When I trying to drive inout signals of DUT Iam getting this error.
Error: (vsim-3053) Illegal inout port connection for port ‘i_sys_clk’.
Please guide me how to drive inout signals from systemverilog testbench.
My systemverilog testbench is as below:
//DUT
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity dut_top is
port (
i_npor : inout std_logic ; – Power-on Reset
i_sys_clk : inout std_logic ; – Core clock
…
);
end entity dut_top;
architecture rtl_top of dut_top is
…
…
end architecture rtl_top;
//interface
`timescale 1ns/1ps
interface tb_sys_interface;
timeunit 1ns;
timeprecision 100ps;
time clock_period = 30.3030ns;
//DVI interface
logic i_sys_clk ; // system clock
...........
...........
...........
initial
begin
i_sys_clk = 0;
forever
begin
#(clock_period/2) i_sys_clk = 1;
#(clock_period/2) i_sys_clk = 0;
end
end
endinterface
//top
module tb_top_wrapper(
tb_sys_interface sys_interface
);
dut_top
uut3
(
.i_npor (sys_interface.i_npor),
.i_sys_clk (sys_interface.i_sys_clk),
.................
................
);
endmodule