How to combine req and rsp sequence item into single class?

UVM
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1

Hi,

In my UVM env, I get req and rsp from monitor. Both req and rsp are of type “tran_seq_item”. I need to combine the req and rsp into single class and send ahead for processing. How do I combine these two seq item classes?

2

In reply to UVM_SV_101:

Please show the code of your req and rsp.

3

In reply to chr_sue:

In reply to UVM_SV_101:
Please show the code of your req and rsp.


//sequence_item_class
class ram_seq_item extends uvm_sequence_item;

   `uvm_object_utils(ram_seq_item)

   function new(string name="ram_seq_item");
      super.new(name);
   endfunction

   rand bit valid;
  rand bit [7:0] addr;
  rand bit [31:0] data_in;
  rand bit cmd;
  rand bit ready;
  rand bit out_valid;
  rand bit [31:0] data_out;
  rand bit [31:0]  tran_id;


endclass

//scoreboard
`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)

class ram_scoreboard extends uvm_scoreboard;

   `uvm_component_utils(ram_scoreboard)

    uvm_analysis_imp_in   #(ram_seq_item, ram_scoreboard) sb_ap_in; //driven thru monitor
    uvm_analysis_imp_out  #(ram_seq_item, ram_scoreboard) sb_ap_out;
  
    ram_seq_item ram_req[int];
    ram_seq_item ram_rsp[int];

    //need to combine req and rsp and send through analysis port
    

    //new constructor
    //code here

    function void write_in(ram_seq_item trans);
     ram_req[trans.addr] = trans;
   endfunction
   
   function void write_out(ram_seq_item trans);
     ram_rsp[trans.addr] = trans;
   endfunction

endclass
4

In reply to UVM_SV_101:

Thanks. But where is your problem?
Your req conatins both input and output data.
But I do not believe you want to randomize valid, ready, out_valid and data_out.
I believe valid, ready and valid_out do not belong to the transaction. They are signals in your virtual interface.
Your req in transaction monitors the data members aadr, daat_in and cmd.
And the rsp especially data_out. There ios nothing to combine.
But I believe you need a tlm_fifo to stote the req.

5

In reply to chr_sue:

In reply to UVM_SV_101:
Thanks. But where is your problem?
Your req conatins both input and output data.
But I do not believe you want to randomize valid, ready, out_valid and data_out.
I believe valid, ready and valid_out do not belong to the transaction. They are signals in your virtual interface.
Your req in transaction monitors the data members aadr, daat_in and cmd.
And the rsp especially data_out. There ios nothing to combine.
But I believe you need a tlm_fifo to stote the req.

Hi,

More information on why I need to combine req, rsp:

  1. Rsp comes OOO out of order so I plan to store req in associative array index- tran_id.
  2. rsp does not have valid data in “addr” signal.
  3. There are more signals in req (I havent shown here in the seq_item), which needs to be send ahead through analysis port

Hence I plan to combine the req, rsp and then send it ahead.

Do you have any suggestion how I can combine these two seq_item and send them through single analysis port?

thnks

6

In reply to UVM_SV_101:

OK, out-of -order is a little bit complicated. The idea with the AA is OK. But I do not understand why you do not have a valid addr in your rsp? The rsp is a copy of the req plus the changes you have to make with respect to the output signal assignments.

7

In reply to chr_sue:

In reply to UVM_SV_101:
OK, out-of -order is a little bit complicated. The idea with the AA is OK. But I do not understand why you do not have a valid addr in your rsp? The rsp is a copy of the req plus the changes you have to make with respect to the output signal assignments.

I could not post everything in my seq_item class due to confidentiality. But the idea is the collect req and rsp and combine them together by matching tran_id.

So what i did was - I created new class “combine_req_rsp” and created 2 instances for req and rsp in it. I use this class in ram_scoreboard and assign the req and rsp I get from tlm port and send it ahead combined through analysis port of type “combine_req_rsp”

8

In reply to UVM_SV_101:

I know near nothing about your design. But I try to explain what I mean.
Below is a fragment of the seq_item of a DDR memory design:

class ddr_seq_item  extends uvm_sequence_item; 

`uvm_object_utils(ddr_seq_item)

rand command_t    command;
rand logic [rsize-1:0] RA;
rand logic [basize-1:0]  BA;
rand logic [3:0]  MA;
rand logic [colsize-1:0] CA;
......
logic [7:0]  data;
logic [7:0]  rsp_DMI;
logic [63:0] rd_data [0:7];
bit error;
....
endclass

All class members with ‘rand’ at the beginning are used to drive the design. They are belonging to the req.
All class members without ‘rand’ at the beginning storing the responses of the design. To make the responses unique we need most of the red data members.
In the driver I’m doing the following

class ddr_driver extends uvm_driver #(ddr_seq_item);
  `uvm_component_utils(ddr_driver)
  virtual ddr_if vif;
  ddr_seq_item    req;
  ddr_seq_item    rsp;
.....
task run_phase(uvm_phase phase);
  `uvm_info(get_type_name(),"run_phase",UVM_MEDIUM)
        reset_procedure();
	forever  
	  fork
            ddr_protocol(...);
	  join  
endtask : run_phase

task ddr_protocol(...);
.....
        seq_item_port.get_next_item(req); // retrieve a req
        // execute the protocol
....
        $cast(rsp, req.clone());
	rsp.set_id_info(req);    // copy the seq_item id from the req to the rsp to indicate  
                                 // both are belonging together
        seq_item_port.item_done(rsp); // sending the rsp back to the sequence
....
endtask

In this case you do not have to execute a seperate step to merge req and rsp and you do not need 2 different seq_items.