How to code the dist statement with array in the constraint

SystemVerilog
,
7

In reply to Manikanta Kopparapu:

I had a typo in my code that I corrected (missing{}'s around the range). but once corrected it works for me. You’ll have to ask the original author of this question, but I believe they wanted either my_addr to be inside the start_/end_range or inside my_exc_array.

module top;
  
class A;
  
  bit [31:0] my_exc_array[$] = {'h1234, 'h5678, 'hABCD, 'hFFFF};
  rand enum {Range, Array} mode;
  rand bit [31:0] my_addr;
  rand bit [31:0] start_addr;
  rand bit [31:0] end_addr;
  constraint my_cons {
     mode dist { Range:=1, Array:=1};
     mode == Array -> my_addr inside {my_exc_array};
    mode == Range -> { my_addr inside {[start_addr:end_addr]};
                        end_addr > start_addr; }
   }
endclass
  
  
  A a = new;
  
  initial repeat(20) begin
    assert(a.randomize());
    $displayh(a.mode.name,, a.my_addr);
  end
endmodule