How to code the dist statement with array in the constraint

SystemVerilog
,
5

In reply to zz8318:

A better way of coding this is using a separate mode variable with a distribution on that mode.

bit [31:0] my_exc_array[$] = {'h1234, 'h5678, 'hABCD, 'hFFFF};
rand enum {Range, Array} mode;
rand bit [31:0] my_addr;
rand bit [31:0] start_addr;
rand bit [31:0] end_addr;
constraint my_cons {
     mode dist { Range:=1, Array:=1};
     mode == Array -> my_addr inside {my_exc_array};
     mode == Range -> { my_addr inside {[start_addr:end_addr]};
                        end_addr > start_addr; }
}

In this way the mode can be used to control sets of constraints.