How to code the dist statement with array in the constraint

SystemVerilog
,
2

In reply to zz8318:



// Code your testbench here
// or browse Examples
class tb;
bit [31:0] my_exc_array[$] = {'h1234, 'h5678, 'hABCD, 'hFFFF};
rand bit [31:0] my_addr;
rand bit [31:0] start_addr;
rand bit [31:0] end_addr;
constraint my_cons {
     end_addr > start_addr;
  my_addr dist { my_exc_array  :/1,            
                    [start_addr:end_addr]     :/1 };
}
  
endclass


module hello;
  tb m1;
  
  initial begin
    m1 = new();
    repeat (10) begin
    if (!m1.randomize()) $display ("Error");
    $display ("start_addr = %h, end_addr = %h,my_addr = %h",m1.start_addr,m1.end_addr, m1.my_addr);
    end
  end
  
  
endmodule