How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation?

SystemVerilog
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21

In reply to prashantk:

BY now you should understand the concepts that I expressed. It’s up to you to do your specific implementation. That concept was basically to use an initial statement in which you define the time in which to start the immediate deferred assertion. That assertion is fired with the forever statement.
The details are now up to you.
Ben

22

In reply to ben@SystemVerilog.us:

yup I got your point , I was just explaining my use case .Thanks :)