In reply to dmitryl:
First, I prefer SystemVerilog over VHDL because it is a much richer language that supports, among other things, associative arrays, dynamic arrays, classes, constraint randomization of variables, RNG (random number generator) stability, see WWW.TESTBENCH.IN - Systemverilog Randomization , and UVM (or a UVM-like) verification environment. It also supports SVA, which I feel is better than PSL. Anyway, you are stuck with VHDL for now.
I have not kept up with the enhancements to VHDL, but they seem slow at being introduced and implemented. Thus, I don’t know if VHDL has a “final”; anyone knows? In any case, why don’t you do your check of (x_glitched > 0) just before you do your report “END OF SIMULATION” severity failure;?
You could use mixed-mode simulation with the testbench in SystemVerilog; however, that signal x has to be visible in the SystemVerilog world; I don’t believe (but I am not sure) if you can poke into a vhdl component from SystemVerilog; perhaps someone can shed light on this.
Ben SystemVerilog.us