How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation?

SystemVerilog
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5

Ben,

My TestBench in VHDL. So, I end it not with Verilog’s $finish, but with the following VHDL statement: report “END OF SIMULATION” severity failure;.
So, will the final procedure work in this case? If it will not, what’s its equivalent for VHDL? How should I end VHDL simulation so that the final procedure will work there as well?

Thank you