How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation?

SystemVerilog
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16

In reply to prashantk:

In reply to ben@SystemVerilog.us:
what could be the assertion …to see that a signal was high throughout the simulation and if it goes low then there should be an error.


assert final (sig) else $display("error message here"); // unclocked, constantly checked
                                 //error message in the Postponed region 
assert property (@(posedge clk) sig) else $display("error message here");
// Checked at posedge of clk

Ben