In reply to ben@SystemVerilog.us:
Hi,
Firstly, thank you for your reply.
I may have confused you with my question but you certainly made things clearer for me. I somehow assumed that retests of the assertion would be marked on the waveform viewer (by an assertion state transition from finished/failed to inactive). I suppose this is not the case since the assertion is tested every clock AND it only lasts one clock. Weirdly, the coverage report also indicates that the assertion was only triggered once.
I will investigate the cover issue further.
Again, thank you for you reply.
Svet