How to check a signal is going high once using assertion

SystemVerilog
4

In reply to nimitz_class:
OOPS! I made a mistake. Should be


 let max= int'(1.0E30); 
    initial ap_a_once_ever: assert property(@ (posedge clk)
         $rose(a) [->1]  |=> strong(a[*max]));

testbench


module top;
    timeunit 1ns;  timeprecision 100ps; 
    bit clk, a, b=1, c=1, reset_n;
    default clocking @(posedge clk);
    endclocking
    initial forever #10 clk = !clk;
    initial begin 
        #100 @(posedge clk) a <=1'b1; 
        // #1000 a <= 1'b0; 
    end 
    let max= int'(1.0E30); 
    initial ap_a_once_ever: assert property(@ (posedge clk)
         $rose(a) [->1]  |=> strong(a[*max]));
      // will fail if a==0 or at end of sim  
    
    initial begin
        #2000; 
      $finish;
    end
  endmodule