How to change the variable size using parameter in UVM using command line arguments?

UVM
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1

I have project that contain some reconfigurable variable like
bit [WIDTH:0] AWADDR;
bit [SIZE:0] WDATA;

how to change width and size of variable using command line arguments ?
i try using compiler drirectives (macros) its possible but its configure at compilation time.
give me some idea about how to change variable size in sequence_item and interface using command line arguments?
or give me some other idea that will help me for changing the size of variable at simulation time not compilation time.

2

In reply to prafulborad3@gmail.com:

Unfortunately, SystemVerilog does not allow you to change the values of parameters at simulation time. Some tools will let you change the values of certain instance parameters on the command line, but with a performance penalty. You need to refer to your tools documentation or contact them directly. This forum is not for tool specific support.

You can use the UVM factory if you want to access some specific parameter specializations. For example, if you have

class my_test #(int WIDTH, SIZE) extends uvm_test;
`uvm_component_param_utils(my_test#(WIDTH,SIZE))
...
endclass

class my_small_test extends my_test#(10,10);
`uvm_component_utils(my_small_test)
...
endclass
class my_big_test extends my_test#(10000,10000);
`uvm_component_utils(my_big_test)
...
endclass

You can switch between UVM_TESTNAME=my_small_test or UVM_TESTNAME=my_big_test when you begin your simulation. You can do similar things with the UVM factory override command switches.