How to bind intesignals of a module to another module

SystemVerilog
,
1

Hi,

How to bind internal signals of a module to another module in systemverilog?


module test();
reg sig1;
endmodule

module test2(input sig2);
endmodule

I need to bind the internal signal of test module sig1 to sig2. How is it possible?

In top file I did something like this but it didnt work.

bind test test2 inst_1(.sig2(sig1));

how can I achieve this?