How to bind an interface with system verilog module?

UVM
9

In reply to justrajdeep:

I see your point, but fundamentally interfaces are supposed to be abstracting individual signals at the bare minimum - in your case it is not doing that. The instantiation is little verbose for a legacy RTL, but then can easily be automated. See what our recently released open-source Go2UVM (www.go2uvm.org) apps generated:

  // Connect TB clk to Interface instance clk

  // DUT instance
  sprot sprot_0 (
    .a(sprot_if_0.a),
    .b(sprot_if_0.b),
    .clk(sprot_if_0.clk),
    .rst_n(sprot_if_0.rst_n),
    .start(sprot_if_0.start),
    .prot_err(sprot_if_0.prot_err),
    .xfer_end(sprot_if_0.xfer_end)
  );

Corresponding Interface (auto-generated)

// Generating SystemVerilog interface for module: sprot
// ---------------------------------------------------------
// Using VW_CLK as a text macro for clock 
// If your clock signal is named other than clk, change the macro below
`define VW_CLK clk
interface sprot_if (input logic `VW_CLK);
  logic   a;
  logic   b;
  logic   rst_n;
  logic   start;
  logic   prot_err;
  logic   xfer_end;
  // End of interface signals 

  // Not showing modport/clocking blocks/assertions

The input to this DVC_Go2UVM app is your RTL top level, in this example it looks like this:


module sprot (input clk, rst_n,
  input start, a, b,
  output logic prot_err, xfer_end);

You can download Verdi plug-in/VC-apps from here: ttp://www.go2uvm.org/download/DVC_GO2UVM_Verdi_2016.05.tar.gz

We also have an integration done to Mentor Questa via PLI. TCL port is on the way.

Regards
Srini
www.go2uvm.org