In reply to chr_sue:
In reply to justrajdeep:
Hi Rajdeep,
the SV standard knows one SV interface construct only. See chapter 3.5 in the standard.
The most simple, but often used, definition looks like this (copied from the standard:
interface simple_bus(input logic logic clk);
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus
It starts with the keyword interface and may hav arguments. In this case it is clk.
Inside the definition there is a list of all variables belonging to this interface.
There is know data direction, because the interface might be connected to at least two blocks. In one of the block the variable might be an input and in the other one an output.
If you want to connect a module to variables internal to the DUT you can use the SV-bind construct. But this is not an SV interface.
Thanks Chris, yes thats what the SV LRM states.